The present invention relates to an all-digital delay locked loop circuit based on a time-to-digital converter, which combines the time-to-digital converter with a phase inversion locking algorithm, and a control method thereof, and more specifically, to an all-digital delay locked loop circuit based on a time-to-digital converter and a control method thereof, which can implement a short locking time, low power consumption, a small chip area and an improved jitter performance, while operating at a very high maximum operating frequency, by combining a phase inversion locking algorithm, operating in a wide operating frequency range by reducing the number of delay elements in a digital control delay line by half in maximum, with a hybrid algorithm including a time-to-digital converter.
A delay locked loop (DLL) is used to improve data transmission speed in an I/O interface between chips in a high-speed integrated circuit such as DRAM, and it is also used for clock data recovery (CDR).
A delay locked loop circuit is generally classified in a method of analogically or digitally adjusting delay of a delay circuit and is divided into two types of an analog delay locked loop circuit and a digital delay locked loop circuit according to such a feedback loop type.
A phase inversion locking algorithm is an algorithm for determining whether or not to use a phase inversion algorithm for a clock input into a delay unit and outputting the input clock or an inverted input clock when such a delay locked loop circuit operates.
If the phase inversion locking algorithm is used, the number of delay units of a delay locked loop can be reduced by half in maximum, and thus the operating frequency range can be extended, the locking time can be reduced greatly compared with an existing method, and low power consumption and a small chip area can be implemented.
A conventional technique has a problem of high power and a long locking time. In addition, a maximum operating frequency is limited due to intrinsic delay of a delay line when the digital delay locked loop operates. A conventional delay locked loop (DLL) using a time-to-digital converter having an advantage of a fast locking time has a problem of a large chip area and high power consumption.
Accordingly, required is development of a delay locked loop circuit having a wide operating frequency range while further increasing the maximum operating frequency and, at the same time, capable of reducing a locking time while implementing fundamental factors such as a high delay resolution, low power consumption, a small chip area and a high jitter performance.